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5th RTD Framework Programme

Success stories - IST

IST (Information Society Technologies)

Project details

Project reference: IST-1999-19007
Acronym: DICTAM
Title: Dynamic Image Computing Using Tera-speed Analogic Visual Microprocessors
Subject Index: Information Processing, Information Systems; Innovation, Technology Transfer
Objectives: Objective: DICTAM aims to produce a new class of image-processing systems based on an optimum, adaptive synergy of Analog Programmable Array Processors (APAPs) and conventional DSPs, including concurrent image transduction and processing by means of Focal-Plane APAPs (FPAPAPs). Substantial advantages in computing speed, system cost, power consumption, and overall quality of the processing functions are expected. The tasks include advanced microelectronic circuit design of mixed-signal APAPs, FPAPAPs and image memory devices, development of optimum hardware/software architectures, of system-specific processing algorithms, and the integration of these basic ingredients into several demonstrators. Within the wide range of applications, the project will focus on real-time dynamic image coding, video authenticity and integrity verification, visual inspection in automated production processes, and motion picture related applications.

Objectives:
DICTAM's objective is to develop new processor architectures, algorithms and integrated circuits for real-time image processing, and to corroborate their advantages using programmable hardware demonstrators applied to selected real-case examples: real-time video compression, image authenticity / integrity verification, and various visual inspection and motion scene evaluation tasks. DICTAM/s success relies on three interlaced objectives:
1) Design of custom Analog Programmable Array Processors (APAPs), Focal Plane APAs (FPAPAPs), and image memory devices with optimum trade-off among area efficiency, accuracy, speed, and power consumption.
2) Development of optimum hardware / software system architectures hosting the new devices as well as conventional DSPs.
3) Development of image processing algorithms for the new processing systems, including adaptive partitioning of the processing tasks among APAPs and DSPs.

Work description:
The technical work has been structured into four workpackages.
WP1 (Design and test of chip-sets): Development of circuit strategies for optimum trade-offs among speed, accuracy, area efficiency, And power consumption of Analog Programmable Array Processors (APAPs), Focal Plane (FPAPAPs), and image memory devices (Analog RAMs) in 0.35 um and/or 0.25um CMOS technologies. Characterisation of CMOS-compatible optical sensors and selection of an optimum alternative for FPAPAPs. Design and test of a 128 x 128 general-purpose APAP chip and 256 x 256 ARAM to be used in a video computing demonstrator. Design and test of a dedicated 128 x 128 FPAPAP CMOS chip with embedded image acquisition to be used in an intelligent visual device demonstrator.

WP2 (Design an test of Analogic Cellular Engine (ACE) boards): Specification, design and test of different hardware platforms hosting alternative combinations of the chips developed in WP1, conventional Digital Signal Processors (DSPs), and conventional image acquisition devices. Development of the software environment required for the control and optimum exploitation of the new ACE architectures. Development of learning and fault-tolerant algorithms for robust applications under the expected residual parametric errors of the analog circuitry.

WP3 (Video Computing): Development of ACE-compatible algorithms for video coding, authenticity, and integrity verification, and of higher level algorithms for selected video computing applications based on the new computing architectures.

WP4 (Embedded Intelligent Visual Devices): Specification of the FPAPAP functionality required for visual-inspection and motion-environment event detection applications. Development of algorithms for environmental surveillance, intelligent scanning, hand-held videoconference, and of higher-level algorithms for visual-inspection applications defined by industrial partners.
Start date: 2000.01.01
End date: 2002.12.31
Duration: 36 months
Project status: Execution
Project cost: 2.11 million euro
Project funding: 1.02 million euro
Programme type: 5th FWP (Fifth Framework Programme)
Subprogramme area: Generic activities: Future and emerging technologies - FET O: Open domain
Contract type: CSC (Cost-sharing contracts)
Prime contractor: Consejo Superior de Investigaciones Cientificas, Instituto de Microelectronica de Sevilla
Organisation type: Research
Country: SPAIN
Region: COMUNIDAD DE MADRID
City: Madrid
Post Code: 28006
Address: Serrano 117
Contact person: RODRIGUEZ-VAZQUEZ, Angel
Telephone: +34-95-4239923
Fax: +34-95-4231832
E-mail: angel@imse.cnm.es
Contractor: Barco Nv, Barco Nv Automation
Organisation type: Other
Country: BELGIUM
Region: VLAAMS GEWEST, WEST-VLAANDEREN, Kortrijk
City: Kortrijk
Post Code: 8500
Address: President Kennedypark 35, PO Box 1
Contact person: VAN DEN BULCK, Pierre
Telephone: +32-56-262632
Fax: +32-56-262690
E-mail: pierre.vandenbulck@barco.com
Contractor: Hungarian Academy of Science, Analogical and Neural Computing Laboratory
Organisation type: Research
Country: HUNGARY
Region: Region not yet available (HUNGARY)
City: Budapest
Post Code: 1111
Address: Kende U. 13 - 17, PO Box 63
Contact person: ROSKA, Tamas
Telephone: +36-11-665644
Fax: +36-11-667503
E-mail:
Contractor: Ecole Polytechnique Federale de Lausanne, Laboratoire de Traitement des Signaux
Organisation type: Education
Country: SWITZERLAND
Region: Region not yet available (SWITZERLAND)
City: Lausanne
Post Code: 1015
Address: Ecublens
Contact person: ZILIANI, Francesco
Telephone: +41-21-6934807
Fax: +41-21-6937600
E-mail: Francesco.Ziliani@epfl.ch
Contractor: ST Microelectronics S.r.l., Soft Computing Group - Catania
Organisation type: Other
Country: ITALY
Region: LOMBARDIA
City: Agrate Brianza
Post Code: 20041
Address: Via C. Olivetti 2
Contact person: LAVORGNA, Mario
Telephone: +39-95-599689
Fax: +39-95-599694
E-mail: mario.lavorgna@st.com
Contractor: Universita di Catania, Dipartimento Elettrico, Elettrico e Sistemistico
Organisation type: Education
Country: ITALY
Region: SICILIA, Catania
City: Catania
Post Code: 95124
Address: Piazza Universita 2
Contact person: FORTUNA, Luigi
Telephone: +39-095-7382307
Fax: +39-095-339535
E-mail: lfortuna@dees.unict.it
Contractor: Katholieke Universiteit Leuven, SISTA/ COSIS
Organisation type: Education
Country: BELGIUM
Region: VLAAMS GEWEST, VLAAMS BRABANT, Leuven
City: Leuven
Post Code: 3000
Address: Groot Begijnhof 59
Contact person: VANDEWALLE, Joos
Telephone:
Fax:
E-mail:
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